This invention pertains to semiconductor devices, and a method for using a layer of conductive material on a grooved surface to obtain a sheet resistance that is lower than that which can be obtained on a flat surface.
In semiconductor devices, including both discrete devices and integrated circuits, it is oftentimes necessary to provide one or more layers of conductive material to serve as an electrical interconnect in addition to one or more metal layers for carrying relatively large amounts of current. A variety of materials have been used as electrical interconnect layers, such as doped polycrystalline silicon, and polycrystalline silicide. The use of polycrystalline silicon as a layer of interconnect is often an attractive choice due to the use of polycrystalline silicon elsewhere in the circuit, for example as gate electrodes of MOS devices. Combinations of polycrystalline silicon and refractory metal silicide layers, often referred to as "polycides", provide an alternative choice, which has the advantages of lower resistivity than single polycrystalline silicon layers and can be formed through selfaligned deposition processing sequences.
The use of polycrystalline silicon and polycides are described, for example, in "a new conduction model for polycrystalline silicon films", Lu et al., IEEE Electron Device Letters, Vol. EDL-2, No. 4, April 1981, pages 95-98: "1 .mu.m MOSFET, VLSI Technology: Part VII - Metal Silicide Interconnection Technology -- A Future Perspective", Crowder et al., IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, April 1979, pages 291-293: and "Interconnections in VLSI", Prabhakar B. Ghate, Physics Today, October 1986, pages 58-66.
FIG. 1 is a cross-sectional view of a typical prior art semiconductor structure including substrate 10, an insulating layer 11, such as silicon dioxide, and electrical interconnect layer 12, which has been patterned to form a desired wiring pattern. Width W of electrical interconnect layer 12 can be made of any convenient size, dependent of course upon the nature of the semiconductor device with which it is used. In other words, it is desired to make width W relatively small so as not to consume very much surface area of the semiconductor device. The thickness t of electrical interconnect layer 12 can also be made within a wide range of sizes, but is typically on the order of 0.3 to 2.5 .mu.m thick. The resistance of an electrical interconnect of length L (measured perpendicular to the cross-sectional view of FIG. 1) is equal to the ##EQU1##
R is the resistance of a length L of electrical interconnect layer 12;
R.sub.s is the sheet resistance of electrical interconnect layer 12;
L is the length of electrical interconnect layer 12; and
W is the width of electrical interconnect layer 12.
In turn, sheet resistance R.sub.s is defined by the following equation ##EQU2## with the thickness of the layer being much less than the probe spacing.
In the prior art structure of FIG. 1, in order to reduce the resistance R of electrical interconnect layer 12 with a given thickness, it is necessary to do one or more of the following things:
1. Increase with W. However, this is undesirable as it requires additional surface area on the semiconductor device.
2. Decrease length L. This is desirable, although length L is dictated by the placement of components within the semiconductor device which are to be electrically connected by electrical interconnect layer 2.
3. Decrease the sheet resistance R.sub.s.
The sheet resistance of a polycrystalline silicon layer can be reduced to about 10 ohms/square. Below this value of sheet resistance, metals such as aluminum or refractory metals, or polycide combinations must be used to achieve even lower sheet resistance values. It is preferred to have polycrystalline silicon as, at least, the first electrical interconnect layer because multiple interconnect layer processes are complicated and the use of polycrystalline silicon as at least first interconnect layer serves to simplify such processes.
Accordingly, it is desirable to minimize the sheet resistance and the overall resistance of an electrical interconnect layer. Prior art techniques allow for the reduction of sheet resistance to within the range of approximately 1 to 10 ohms/square, but sheet resistance of typical electrical interconnect layers cannot be reduced lower due to geometrical size and process related limitations. Therefore, prior art techniques for fabricating electrical interconnect layers have a lower limit of electrical resistance which has heretofore not been broken.